1. Field of the Invention
The present invention relates to a solid-state image pickup device and an image pickup system, and more particularly to an amplifying type solid-state image pickup device and a camera, both provided with a photoelectric conversion pixel unit composed of a plurality of arranged pixels, each equipped with at least a photoelectric conversion unit and a transistor for amplifying and outputting a signal from the photoelectric conversion unit.
2. Related Background Art
As a solid-state image pickup device, a CCD has been conventionally used in many cases because of the goodness of the SN ratio thereof. However, on the other hand, the development of the so-called amplifying type solid-state image pickup device having the advantages of the easiness of handling and the smallness of the power consumption thereof has been also performed. The amplifying type solid-state image pickup device is a solid-state image-pickup device of the type of leading the signal charges stored in light-receiving pixels to the control electrodes of the transistors provided to the pixel units and outputting an amplified signal from the main electrode. To put it concretely, as the amplifying type solid-state image pickup device, there are an SIT image sensor using SIT's as amplifying transistors (A. Yusa, J. Nishizawa et al., “SIT image sensor: Design consideration and characteristics,” IEEE trans. Vol. ED-33, pp. 735-742, June 1986), BASIS using bipolar transistors (N. Tanaka et al., “A 310K pixel bipolar imager (BASIS),” IEEE Trans. Electron Devices, vol. 35, pp. 646-652, May 1990), CMD using JFET's in which control electrodes are depleted (Nakamura et al., “Gate Storage Type MOS Phototransistor Image Senso”, The Journal of the Institute of Television Engineers of Japan, 41, 11, pp. 1075-1082 November, 1987), a CMOS sensor using MOS transistors (S. K. Mendis, S. E. Kemeny and E. R. Fossum, “A 128×128 CMOS active image sensor for highly integrated imaging systems,” in IEDM Tech. Dig., 1993, pp. 583-586.), and the like.
In particular, a CMOS sensor has good matching with a CMOS process, and peripheral CMOS circuits can be made to be on-chip. Accordingly, energy has been thrown to the development of the CMOS sensor. However, as a common problem of these amplifying type solid-state image pickup devices, the following problem can be cited. That is, since the output offset of the amplifying transistor provided to each pixel differs from each other, a fixed pattern noise (FPN) is superposed on a signal of the image sensor. For reducting the FPN, various signal readout circuits have been devised conventionally.
Another problem of the amplifying type solid-state image pickup device relates to operation timing. The read of pixel signals of this type of image sensor is performed to one row at a time, and a horizontal transfer operation follows after the read of the data of one row. Consequently, signal storage operation of a pixel shifts for every row. The reason is that the signal storage operation of the pixels in one field is completed by the read of the pixel signals of the field. Therefore, the timing shift between the first row and the last row is almost one field time. On the other hand, in a CCD, all pixel signals are transferred to vertical CCD's all at once, and the storage operation of the CCD pixels is completed and started by this simultaneous transfer. Consequently, the operations of the CCD pixels are simultaneous. When a subject moving at a high speed is photographed, the operation timing shift of the amplifying type image sensor appears as the distortion of an image.
With an object of improving the problem, Japanese Patent Application Laid-Open No. S58-125982 and No. H02-65380 severally propose an image sensor equipped with an analog frame memory composed of memory cells each consisting of a MOS switch and a capacitance. In each of the proposed sensors, pixel signals are transferred to corresponding memory cells for a short time without performing horizontal transfer operations, and then the read of memory signals is performed over almost one field period while performing horizontal transfer. Thereby, the operation timing shift is remarkably shortened.
Moreover, Japanese Patent Application Laid-Open No. 2003-51989 discloses a solid-state image pickup device equipped with an amplifier having a gain exceeding 1, which is provided to each row.
FIG. 8 shows a circuit diagram of a conventional image sensor. In the drawing, reference numeral 1 denotes an amplifying type pixel including at least a photodiode and an amplifying transistor. FIG. 9 is a circuit diagram of a typical CMOS sensor pixel as an example of the amplifying type pixel in FIG. 8. A conventional technique will be described with reference to FIGS. 8 and 9.
As shown in FIG. 9, a pixel 1 is composed of a photodiode 18, a transfer transistor 20 controlled by a pulse φTX, a floating diffusion (FD) portion 19, to which a signal charge from the photodiode 18 is transferred, an amplifying transistor 21, the gate of which is connected to the FD portion 19, a selection transistor 22 for pixel selection, which is controlled by a pulse φSEL, and a reset transistor 23 controlled by a pulse φRES. The selection transistor 22 is connected to a vertical pixel output line 2, and the vertical pixel output line 2 is connected to a current supplying transistor 7 controlled by a pulse φG.
When the pulse φSEL turns to a high level and the selection transistor 22 becomes a conduction state, a current is supplied from the current supplying transistor 7 to the amplifying transistor 21 of the pixel 1 selected by a scan circuit 4 as shown in FIG. 8, and the amplifying transistor 21 operates as a source follower to output its output voltage to the vertical pixel output line 2. The floating diffusion (FD) portion 19 is first reset by the application of the reset pulse φRES to the reset transistor 23, and an output corresponding to the FD potential appears on the vertical pixel output line 2. Although the reference voltage on the side of the vertical pixel output line 2 is dispersed owing to the dispersion of the threshold voltage of the source follower among each pixel, a uniform clamp voltage VR becomes the reference voltage on the side of the vertical memory output line 11 since a clamp transistor 6 and a switch transistor 8 are conducted by pulses φC and φSH. Next, the clamp transistor 6 is made to be in an off-state, and the vertical memory output line 11 side of a coupling capacitor 5 is made to be in a floating state. Then, a pulse φTX is applied to the transfer transistor 20. Thereby, the signal charge existing in the photodiode 18 is transferred to the FD unit 19. The fallen portion of the FD voltage proportional to the signal is read to the vertical pixel output line 2, and is further transferred to the vertical memory output line 11 through the coupling capacitor 5. The signal voltage is written in memory cell capacitance 9 by applying a pulse to a write transistor 10 through a memory selection line 12. The memory selection line 12 is successively selected in accordance with a memory scan circuit 13. The signal voltage written in the memory cell capacitance 9 does not include the fixed pattern noise (F. P. N.) of a pixel by the clamp operation described above. That is, although the signal corresponding to the signal charge existing in the photodiode 18 is read to the vertical pixel output line 2 (the read signal contains a noise component), the noise component is beforehand read to the vertical pixel output line 2. Therefore, the potential change quantity of the vertical pixel output line 2 is based on only a signal component, and the signal transferred to the vertical memory output line 11 through the coupling capacitor 5 is one from which the noise component has been reducted. After the signal transfer from the pixels of every row to each memory has been completed, signal read of each memory is performed as follows.
First, the pulses φC and φSH are applied to the clamp transistor 6 and the switch transistor 8, respectively, and thereby the vertical memory output line 11 is reset to the potential VR. After making the switch transistor 8 in the off-state, the signal voltage stored in the capacitance 9 of the memory cell of the row selected by the memory scan circuit 13 is transferred to the vertical memory output line 11. The signal voltage on the vertical memory output line 11 is transferred in order to a horizontal output line 14 by a horizontal scan circuit 16 through a switch transistor 15 which is scanned by the horizontal scan circuit 16. The signal voltage on the horizontal output line 14 is amplified by an amplifier circuit 17, and is read as a sensor output. A memory signal is thus read by the memory scan circuit 13 and the horizontal scan circuit 16. The transfer time of a pixel signal to a memory is greatly shortened in comparison with the read time of a general CMOS sensor without any memory. Consequently, the defect pertaining to the time difference of the storage operation timing of a pixel can be fully improved.
However, the amplifying type image sensor with a frame memory by the conventional technique has a problem pertaining to the SN ratio. That is, a signal voltage read from a pixel is greatly decreased by a division of the signal on a transfer path of the signal, and further the signal voltage is influenced by thermal noises on the transfer path. The division of a signal takes place by receiving capacitance division at the time of the transfer of the signal. The division of a signal first occurs at the time of the transfer from the vertical pixel output line to the memory capacitance 9, and second occurs at the time of the transfer from the memory capacitance 9 to the horizontal output line 14. The thermal noises occur at the time of resetting a signal path, namely the coupling capacitor 5, the vertical memory output line 11, the memory capacitance 9 and the horizontal output line 14. The noise charges are expressed by (kTC)1/2, where k denotes a Boltzmann's constant, T denotes an absolute temperature, and C denotes the capacitance at a part to be reset.